1. Field of the Invention
The present invention relates to a system LSI having a core CPU and, more particularly, to a system LSI capable of executing the dynamic clock control from the side of an application program.
2. Description of the Related Art
In case of battery-powered devices, for instance a mobile telephone, which belong to the application field of a microcontroller constituted by means of a system LSI, it seems that many of them are still requested to improve themselves such that their consumption of electric power (referred to simply as “power” hereinafter) is reduced as low as possible for the sake of their users' convenience and benefit, and there have been developed various techniques for responding to such request. Owing to these techniques, it has become possible to reduce the power consumption of the entire system, though gradually, by properly changing the clock speed corresponding to the need, for instance by supplying the high-speed clock when the high speed processing is necessary and supplying the low-speed clock when the wait state is needed. In the recent years, in almost all application fields, an application specific integrated circuit (ASIC) is provided for the microcontroller constituted by means of the system LSI. In the case of the system into which the ASIC is built, in order to extend the battery life, the power reduction as well as the matters related thereto are requested to be described in the specification of the system, and it becomes not rare that such low power consumption technique is incorporated into the core CPU of the system.
To begin with, a core CPU ST7 (referred to as “ST7 core” hereinafter), a product of a U.S. firm “ST Microelectronics” will be explained as an example of a conventional core CPU with reference to FIGS. 9 and 10 of the accompanying drawings. FIG. 9 is a block diagram for explaining a clock control circuit 40 of the ST7 core while FIG. 10 is an illustration for explaining the clock operation mode of the ST7 core.
As shown in FIG. 9, an oscillation portion 41 includes two oscillation terminals OSC1 and OSC2 and is connected with an oscillator such as a quartz oscillator through these oscillation terminals, thereby generating clock signals. A clock correction portion 42 is made up of a clock filter 43 and a clock rearrangement portion 44. The clock filters 43 removes the clock in which a spike noise or the like is mixed, and rearranges the clock in a predetermined wave forms. If the clocks are sparsely lined as a result of the above rearrangement of wave form thereof, the rearrangement portion 44 operates to narrow the frequency bandwidth of the clock.
A main clock control circuit 45 is made up of a setting register 46 and a clock frequency dividing portion 47. The setting register 46 sets the frequency division ratio of the clock to be 1/4, 1/8, 1/16, and 1/32. The frequency divided clocks fcpu are supplied to the ST7 core and peripheral devices, and are outputted from the I/O terminal CLKOUT to the external portion through an I/O switching portion 48.
The ST7 core is operable in four kinds of clock operation modes as shown in FIG. 10, under the control of the above clock control circuit 40. To put it more concretely, the ST7 core operates at the frequency of 1/2 of the oscillation frequency in the high-speed operation mode. In the low-speed operation mode, it operates at the frequency of 1/4, 1/8, 1/16, and 1/32 of the oscillation frequency, respectively. In the wait mode, the clock of the CPU is halted while peripheral devices are in operation. In the halt mode, the oscillation per se halts so that the power consumption of the ST7 core is then minimized. Like this, if each operation mode is selectively used in correspondence with the processing by the CPU, a considerable amount of the power consumption can be saved in total.
On one hand, in case of constituting a microcontroller by means of the system LSI, there are some cases where the low power consumption technique is incorporated in the core CPU. An ARM920T (referred to as ARM core hereinafter), a product of a British firm “ARM”, may be a good example of such core CPU. In case of the ARM core, it is premised that a power management portion is formed on the side of the system LSI.
There are two reasons why the ARM core adopts the constitution like the above. The first reason is that if the clock control mechanism is built in the core CPU side, a certain restriction is given to the design of the system LSI, as a result of which the core CPU would come to lose versatility thereof. On the side of the system LSI using the core CPU, there might take place a case where the clock drops its speed down and halts, eventually. In such case, it would become necessary to detect and examine such state and to adjust the timing of the internal memory, the internal timer, and so forth.
The second reason is as follows. The ARM core is provided with a joint test action group (JTAG) interface test terminal, and transmits the internal state of the core CPU to the external portion through an in-circuit emulator (ICE), and operates the debugger, thereby giving convenience to the development of the application program. Consequently, the clock change on the core CPU side results in restriction of such use of the test terminal. Therefore, in order to effectively carry out the power management free from such restriction as mentioned above, it is preferable for them to provide the power management portion not on the side of the core CPU but on the side of the system LSI, thereby achieving the total power management.
In recent years, the system LSI has been sophisticated more and more and it becomes so difficult for the core CPU to directly and quickly respond to various demands coming from ASIC only by the core CPU itself. Then, in order to comply with the above problem, it would be considered to provide a versatile microcontroller mounting the same core CPU thereon. In other words, it is the thought of collecting common elements which are usually used by the system LSI, for instance, peripheral devices of the CPU, memory architectures and so forth, and have the basic function of executing an operating system (OS) at real time, and of presenting a versatile microcontroller provided with the elements and function as described above.
In order to achieve a total power management by mean of a versatile microcontroller like this, it is necessary for the versatile power management to be carried out taking account of not only the core CPU but also the inherent function of the application.
In the power management by the prior art microcontroller, however, the clock is just simply changed similar to the case of the ST7 core as mentioned above. In case of the ST7 core, as shown in FIG. 10, there are just simply changed the four operation modes which are the high-speed operation mode, the low-speed operation mode, the wait mode and the halt mode. However, when the power management portion is provided not on the side of the core CPU but on the side of the system LSI, it is demanded that the clock of the core CPU and that of the system LSI have to be separately controlled. Consequently, it is not possible to carry out a fine control by means of the simple model like this.
Furthermore, it has been tried to dynamically control the clock from the application program side. For instance, in case of the ST7 core, the circuit related to the clock control is controlled by means of an assembler language which can be directly controlled. However, the clock control by using the assembler language is apt to receive many restrictions from the point of view of the application program development. Accordingly, it is preferable, if possible, to provide a flexible interface constituted by using the high-level program language like the C language that is usually adopted in the current software development. Unfortunately, however, there has been no support allowing a real power management by using the programming language like this.